As transistor technology continues to scale and integration density increases, one performance limiter of an integrated circuit (“IC”) chip will be heat management and/or removal. Not only does heat affect device operation, but it may also affect end user usage patterns. Further, because the reliability and performance of transistors and interconnects depend on operating temperatures, the need to cool electronics and diminish device hot spots has never been greater. With the continued scaling of device features and increased power density, chip cooling has become increasingly difficult and costly.
One method of continued scaling includes three-dimensional (“3D”) stacking of chips used to form a stacked IC package. 3D die (e.g., silicon chip die) stacking increases transistor density and chip functionality by vertically integrating two or more die. 3D integration also improves interconnect speed by decreasing interconnect wire length, enables smaller system form factor, and reduces power dissipation and crosstalk.
Motivations for 3D integration include reduction in system size, interconnect delay, power dissipation, and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products implement improved performance and increased device packing density realized by 3D stacking of chips (e.g., using wire bonds), such technologies are not suitable for high-performance chips due to ineffective power delivery and heat removal. For example, high performance chips are projected to dissipate more than 100 W/cm2 and require more than 100 A of supply current. Consequently, when such chips are stacked, challenges in power delivery and cooling become greatly exacerbated.
Systems and methods for cooling 3D ICs using microfluidic interconnects have been proposed by the inventors of the present application, e.g. U.S. Pat. No. 7,928,563, which is incorporated herein by reference in its entirety as if fully set forth below. Unfortunately, fabrication of these conventional 3D ICs can be a tedious process requiring separate steps for fabrication of fluidic and electrical interconnects. Another disadvantage of conventional cooling methods is the need for polymer sockets to seal fluidic interconnects, thus necessitating additional space between adjacent chips in a stack. Yet another disadvantage of conventional cooling methods is the need for an epoxy-based sealant/underfill to be applied to the chips creating a hermetic seal, which limits the possibility of reworking, i.e. disconnecting and/or rearranging, chips once the 3D stack is assembled.
Accordingly, there is a desire for chips, 3D ICs, and methods of fabricating same, which address the disadvantages associated with conventional chips and fabrication methods. Various embodiments of the present invention address these desires.